The vast majority of electronic devices include at least one microcontroller or microprocessor that controls the operation thereof. In order to perform the desired functionality a microcontroller will execute code or executable instructions for performing specific operations. The microcontroller may also retrieve data for performing these operations. The code and data are stored in the computer readable memory device. Increasingly, manufacturers are using solid-state nonvolatile memory devices such as flash memory devices, e.g. NAND flash memory devices or NOR flash memory devices, as the computer readable memory devices.
One issue that arises with flash memory devices, however, is that read-inability errors are more commonly observed in flash memory devices, and especially in NAND flash memory. Read-inability errors can be permanent such as a bad block error, e.g. a bit within the block has been physically damaged, or temporary such as a data retention error or a read disturb error. Manufacturers of devices having non-volatile memory, such as flash memory devices, utilize error correction codes (ECC) to correct bit errors that occur in the memory device. During normal operation of the device when data is written to a memory device, ECCs are generated for that data by the hardware of the memory device and automatically stored with the data. On subsequent reads, the ECC is read back and used by the hardware to correct errors in the data. ECC codes can be parameterized during the hardware design phase to correct a fixed number of errors while using a given amount of storage overhead. Once ECC parameters are selected and implemented in the hardware, the ECC circuitry cannot be modified to correct more errors than the ECC scheme was originally designed for. When a read error occurs during normal system operation, it may be determined that there are more errors in the data than the ECC algorithm can fix. In these situations, the data is not recoverable. Thus, if the system designer requires stronger ECC algorithms than are implemented in the hardware ECC, the hardware ECC can be disabled and a stronger ECC algorithm can be executed by the microcontroller of the device. However, these ECC algorithms may decrease the overall performance of the microcontroller when reading and writing to the flash memory device.
As mentioned above, some errors may be temporary errors. Temporary errors in the data stored in the flash memory device accumulate over time due to interference from internal and external events that occurred during the normal system operation. Temporary errors occur in memory cells that do not have any physical defects. Because the memory cells are not defective, the correct data can be restored by performing a refresh operation on the block or page of data, which will include ECC-based error corrections, followed by a rewrite of the corrected data.
Permanent errors, however, cannot be fixed by refresh operations. Unlike temporary errors, permanent errors are typically caused by physical defects in the memory. While the ECC can correct permanent errors, the amount of errors that the ECC can correct is limited. Thus, there is a need for a more efficient way to handle permanent errors, as well as temporary errors, in memory devices, such as a flash memory device.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.